This course aims to provide students with the theoretical foundations and practical skills needed to design and implement digital filters. Students will learn about filter specifications, types, and the trade-offs involved in digital filter design. They will also gain hands-on experience with tools for implementing filters in software and hardware.

This course introduces AESE students to the full design cycle on Field-Programmable Gate Arrays (FPGAs). Starting from the evolution of programmable logic devices (PROM → PAL → GAL → CPLD → FPGA), the course covers FPGA internal architecture (CLBs, LUTs, flip-flops, routing fabric, BRAM, DSP slices, and clock management), and compares FPGAs against ASICs and microcontrollers across key design criteria. Students will learn to select the appropriate FPGA resource for a given application, and apply clock domain crossing mitigation techniques. Practical sessions use Xilinx Vivado to implement and test real hardware designs on FPGA boards. By the end of this course, students will be able to design, analyze, and prototype custom hardware solutions in response to the functional and timing requirements of industrial or autonomous embedded systems applications.

Credits: 3 — Coefficient: 3 — Module Average: 20% Continuous Assessment | 20% Lab Work | 60% Final Exam